1. Field of the Invention
The present invention relates generally to single-poly non-volatile memory (NVM) devices. More particularly, the present invention relates to single-poly electrical programmable read only memory (EPROM) devices, and program, read and erase methods for operating such device.
2. Description of the Prior Art
Non Volatile Memory (NVM) is arguably one of the most popular electronic storage mediums. The basic conception is the memory, which retains data stored to it when powered off. This memory family has several members (ROM, OTP, EPROM, EEPROM, flash) with varying degrees of flexibility of use differentiating them.
Depending on the times of program and erase operations of a memory, the NVM can be further cataloged into multi-time programmable memory (MTP memory) and one-time programmable memory (OTP memory).
MTP memory, such as EEPROM or flash memory, is repeatedly programmable to update data, and has specific circuits for erasing, programming, and reading operations. Unlike MTP memory, OTP memory is one-time programmable and has circuits for programming and reading operations without an erasing circuit, so the circuit for controlling the operations of the OTP memory is simpler than the circuit for controlling the operations of the MTP memory.
In order to expand the practical applications of the OTP memory, an erasing method used in EPROM (such as ultraviolet illumination) is attempted to erase data stored in OTP memory. In addition, a simple circuit is designed to control OTP memory and simulate updateable ability like MTP memory.
Traditionally, either an MTP memory cell or an OTP memory cell has a stacked structure, which is composed of a floating gate for storing electric charges, a control gate for controlling the charging of the floating gate, and an insulating layer (such as an ONO composite layer composed of an silicon oxide layer, a silicon nitride layer, and an silicon oxide layer) positioned between the floating gate and the control gate. Like a capacitor, the memory cell stores electric charges in the floating gate to get a different threshold voltage Vth from the memory cell stores no electric charges in the floating gate, thus storing binary data such as 0 or 1.
The stacked gate structure of non-volatile memory makes the advanced logic process more complex and more costly because additional polysilicon deposition, thermal budget, and difficult lithograph and etching steps are involved. The thermal budget also affects the electrical property of the logic devices. Especially for most of the leading logic technologies, dozens of transistors performance will be changed due to the introduce of extra thermal budget. It is very hard to turn back to the original target one for the embedded nonvolatile memory process. And moreover, the re-adjustment of the logic devices may seriously delay the product developing time schedule.
For all worldwide semiconductor companies, a simple nonvolatile memory solution is desired in advanced logic process. No additional mask steps, no ultra high voltage operation, fully compatible to standard logic process are strongly requested and preferred. No additional mask step means that only logic transistors devices can be adopted to serve as a non-volatile memory device. No ultra high voltage operation means that extra high voltage device process and stacked floating gate non-volatile memory are excluded in the non-volatile memory candidates for advanced logic process nodes. Single poly non-volatile memory will be a more suitable NVM solution than the double poly stacked gate one in the advanced technology nodes.
On the other hand, many innovative inventions are directing the nonvolatile memory development to use the single poly solution. Single-poly non-volatile memory is regarded as a semiconductor process which is more compatible with standard CMOS processes and is thus more easier utilized in embedded memory such as mixed-mode circuits or embedded NVM memory of micro-controllers.
U.S. Pat. No. 5,761,126 describes a single poly EPROM cell that utilizes a reduced programming voltage to program the cell. The programming voltage of single-poly EPROM cell is reduced by eliminating the N+ contact region which is conventionally utilized to place a positive voltage on the N-well of the cell, and by utilizing a negative voltage to program the cell. The negative voltage is applied to a P+ contact region formed in the N-well which injects electrons directly onto the floating gate of the cell.
U.S. Pat. No. 6,930,002 describes a method for programming single-poly EPROM at low operation voltages. The single-poly EPROM cell includes a P-channel floating-gate transistor formed on an N well of a P type substrate, and an N-channel coupling device. The P-channel floating-gate transistor has a P+ doped drain, P+ doped source, a P channel defined between the P+ doped drain and P+ doped source, a tunnel oxide layer on the P channel, and a floating doped poly gate disposed on the tunnel oxide layer. The N-channel coupling device includes a floating poly electrode, which is electrically connected to the floating doped poly gate of the P-channel floating-gate transistor, and is capacitively coupled to a control region doped in the P type substrate.
U.S. Pat. No. 6,025,625 describes a single-poly EEPROM cell structure and array architecture. The single-poly EEPROM cell comprises an inverter and a capacitive coupling area. The inverter is formed by: a p-well formed in a substrate; a gate structure formed atop the p-well and being formed from a thin gate oxide layer underneath a conductive layer; an n-base formed adjacent to a first edge of the gate structure and within the p-well; a p+ structure formed within the n-base; and a n+ structure adjacent a second edge of the gate structure and within the p-well.
The above-described prior art single-poly floating gate non-volatile memory has several drawbacks. First, the prior art single-poly floating gate non-volatile memory unit occupies larger chip area. Hitherto, the miniaturization of single-poly floating gate non-volatile memory unit for advanced 90-nano or below semiconductor process is still a huge challenge for the semiconductor manufacturers.
With the moving to next generation of the logic process, both the operation voltages and gate oxide thickness shrink. For example, the thickness of the gate oxide ranges between 50 and 60 angstroms for I/O transistors in 90-nano processes. The shrunk gate oxide thickness impedes the development of the floating gate based single-poly MTP memory because thin tunnel oxide will affect long term charge retention, while increasing tunnel oxide thickness is not compatible with logic process. The tunneling oxide with the physical oxide thickness larger than 70 angstroms is regarded as a basic requirement for the long term charge retention reliability in the floating gate non-volatile memory devices.
Conventional methods for programming the single-poly floating gate EPROM are operated at voltages that are relatively higher than Vcc (3.3V input/output supply voltage in 90 nm logic process), for example, a high couple well voltage of about at least 8˜10V that is high enough to establish adequate electric field strength across the tunnel oxide. Thus, additional high-voltage circuitry and high-voltage devices are required. Operating at high voltages also adversely affects the reliability of thin gate dielectric having a thickness of 50˜60 angstroms in the peripheral logic transistors if we don't want to introduce additional high voltage processes. Further, conventional single-poly floating gate EPROM technology needs a large cell size and a high voltage to capacitively couple the floating gate for programming the memory cell.
Therefore, the key to a successful next generation non-volatile memory device will rely on the low voltage operation and adoption of an innovative idea instead of floating gate technologies.